1. Field of the Invention
The present invention relates to electronic devices and, more particularly, to a package having a redistribution interposer between a chip and a lead frame.
2. Prior Art
U.S. Pat. No. 4,461,924 discloses a semiconductor chip connected by wire leads to a lead frame with a metal casing enclosing the chip and wire leads. Other semiconductor packages are disclosed in U.S. Pat. Nos. 4,888,449; 4,897,508; 4,939,316; 5,013,871; 5,066,368; 5,073,521; 5,098,864; 5,103,292; and 5,015,803. Leads and contact areas connected in series are disclosed in U.S. Pat. Nos. 5,077,595; 5,124,783; 4,480,013; 4,631,820; 4,754,317; 4,774,635; 4,771,330; 4,800,419; and 4,903,114. Pin grid array (PGA) packages are also known in the art as disclosed in U.S. Pat. Nos. 4,630,172; 4,677,526; 4,816,426; 4,750,092; 4,890,152; 4,823,234; and 4,618,739.